1. Field of the Invention
The present invention relates to an A/D converter that converts voltage data into digital voltage data, and particularly, to a successive approximation A/D converter.
2. Description of the Related Art
A/D converters are used for various electronic circuits and various applications. Along with the development of the electronic circuit technology in recent years, the processes of the electronic circuits in which the A/D converters are used are becoming increasingly complex, while the reliability expected for the A/D converters is also increasing. Especially in the A/D converters and the like used as on-vehicle electronic circuits, the reliability expected for the A/D converters needs to be increased.
FIG. 15 is a block diagram of a general successive approximation A/D converter. A successive approximation A/D converter 100 includes a timing control circuit 2, a sample-hold circuit 3 that samples and holds an analog input voltage Vin, a comparator 4 that compares the analog input voltage Vin held in the sample-hold circuit 3 and a reference voltage Vref, a successive approximation register 50 that generates comparison codes for determining a reference potential for the next comparison based on the comparison result of the comparator 4, and a D/A converter 6 that generates the reference voltage Vref based on the result of the successive approximation register 50. FIG. 15 illustrates a six-bit A/D converter. The comparison codes D5 to D0 provided for the D/A converter 6 serve as an A/D conversion result at the end of the A/D conversion.
In regard to such a successive approximation A/D converter, a successive approximation A/D converter is described in Japanese Patent Laid-Open No. 2000-049609 that can increase the reliability of the converted values even if an erroneous comparison and judgment is made during conversion due to external noise or the like. FIG. 16 is a schematic diagram modified the successive approximation A/D converter shown in Japanese Patent Laid-Open No. 2000-049609. It is to be noted that the same constituents as those shown FIG. 15 are denoted by the same reference numerals.
A potentially erroneous bit decision circuit 130 sequentially compares the value of the lowest bit of the successive approximation register 50, the value being the result of the A/D conversion of the analog input signal Vin, and the values of the subsequent higher bits. When the value of the higher bit has become different first from the value of the lowest bit, the bit is a potentially erroneous bit. A comparison decision circuit 140 judges whether the digit position of the potentially erroneous bit is below the digit position of the tolerable error bit set up in a tolerance setting register 160. If the digit position of the potentially erroneous bit is above the digit position of the tolerable error bit, the A/D conversion is determined to be erroneous, and a control signal for requesting reconversion is outputted to the control circuit 2 and the like.
However, the value of an arbitrary bit of the successive approximation register may be inverted due to external noise or software error. If the inverted bit is detected as a potentially erroneous bit, the A/D converter shown in FIG. 16 determines that the conversion result is erroneous and digitally converts the analog input signal Vin again. However, if the data is inverted after the comparison result is provided to the arbitrary bit of the successive approximation register, the A/D converter shown in FIG. 16 determines that the A/D conversion has been conducted normally and outputs a wrong conversion result unless the bit is detected as a potentially erroneous bit. Even if the bit is detected as a potentially erroneous bit and reconversion is performed, the potentially erroneous bit decision is made after the conversion result is set up to every bit of the successive approximation register. Therefore, it takes time to obtain the correct conversion result.